An Efficient Logic Emulation System

The Realizer is a logic emulation system that automatically configures a network of Field-Programmble Gate Arrays (FPGA’s) to implement large digital logic designs. Logic and interconnect are separated to achieve optimum FPGA utilization. Its interconnection architecture, called the partial crossbar, greatly reduces system-level placement and routing complexity, achieves bounded interconnect delay, scales Iinearly with pin count, and allows hierarchical expansion to systems with hundreds of thousands of FPGA devices in a fast and uniform way. An actual multiboard system has been built, using 42 Xilinx XC3090 FPGA’s for logic. Several designs, including a 32-bit CPU datapath, have heen automatically realized and operated at speed. They demonstrate very good FPGA utilization. The Realizer has applications in logic verification and prototyping, simulation, architecture development and special-purpose execution.